In computing applications, processors may be communicatively linked to memory units, and processors may write data to and read data from those memory units while executing instructions. Events such as faults may cause a memory unit, or portions of a memory unit, to fail and corrupt data stored therein. The processor's use of such corrupted data may cause an error either by forcing the processor to halt the execution of a program or by allowing the processor to continue processing using incorrect data. An error due to corrupted data may go undetected by the processor.
When a processor writes data to memory, that data may be encoded according to an error correcting code in order to make the data discernible in the event of a memory fault. Encoding a data word through the use of an error correcting code increases the storage space necessary for the data word because check bits, also known as parity bits, are appended to the data bits. The data bits and check bits together constitute a code word. A linear block code (LBC) is a type of error correcting code in which a one-to-one mapping exists between data words and corresponding code words, and LBCs may be referred to using (n, k) notation, where n is the total number of bits in the code word and k is the total number of data bits. An (n, k) LBC has n-k check bits. When the processor reads data from memory, a stored code word may be used to generate a syndrome vector, which may be used to detect and to correct errors in the stored data bits. A corrected version of the stored data bits may then be sent to the processor in response to the memory read request.
Error correcting and detecting codes allow processors to continue executing properly in the face of some memory unit failures by building redundancy into data storage, although a code may detect more errors than it is able to correct. Due to the necessity for increased storage and increased data processing, error correcting codes may require increased hardware resources and may slow the execution rate of instructions on a processor. Error correction and detection may be implemented in field-programmable gate arrays (FPGAs) having partially pre-configured logic circuitry, such as look-up tables (LUTs) allowing only four or fewer inputs per table, and in such an implementation, every additional level of logic required by a particular error correcting code may increase the processing time necessary to write encoded data to memory or to read corrected data from memory.
In real-time systems, such as aerospace systems, the added expense of error correcting codes may be particularly difficult for a system to bear. A real-time system fails if it does not comply with specified real-time deadlines. For example, an aircraft may have to compute its position relative to the ground a particular number of times per second to continue to operate safely, and such a computation would be carried out by a real-time system on the aircraft. The added expense of error correction in a real-time system may not only cause delay in execution but also system failure due to missed deadlines. However, without some form of error correction, a real-time system is also vulnerable to system failure upon even the mildest of memory faults.